Fully differential CMOS phase-locked loop

ABSTRACT

The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (C 3 MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C 3 MOS logic.

CROSS-REFERENCES TO RELATED APPLICATION(S)

[0001] This application is a continuation of U.S. patent applicationSer. No. 09/919,636, which is a continuation-in-part application of U.S.patent application Ser. No. 09/540,243, filed on Mar. 31, 2000, now U.S.Pat. No. 6,526,113 B1, which claims the benefit of priority from U.S.Provisional Patent Application Serial No. 60/148,417, filed on Aug. 11,1999, the disclosures of which are hereby incorporated by reference inits entirety for all purposes.

[0002] The continuation-in-part application U.S. patent application Ser.No. 09/919,636 also claims the benefit of priority from U.S. ProvisionalPatent Application Serial No. 60/238,317 filed on Oct. 4, 2000, thedisclosure of which is also hereby incorporated by reference in itsentirety for all purposes.

BACKGROUND OF THE INVENTION

[0003] The present invention relates in general to integrated circuits,and in particular to method and circuitry for implementing an improvedphase-locked loop (PLL) in complementary metal-oxide-semiconductor(CMOS) technology.

[0004] The convergence of various high speed data communicationtechnologies (e.g., Ethernet, fiber channel, IEEE firewire links) intothe gigabit domain has focused the efforts of integrated circuitdesigners on developing high speed circuit techniques for processingbroadband signals. Similarly, efforts directed at developing low costand low power dissipation circuits have been driven by the explosivegrowth in wireless media for voice and data communications.

[0005] A circuit block that is commonly found in voice and datacommunication applications is a phase-locked loop (PLL). The primaryfunction of the PLL is to maintain a fixed phase relationship between aninput (e.g., clock) signal and a reference signal. A PLL designed for adigital application typically includes a phase and/or frequencydetector, a charge pump, a loop filter, a voltage controlled oscillator(VCO), and an (optional) divider. The phase detector determines thephase differences between an input signal (i.e., an input data stream oran input clock) and a reference signal derived from the VCO, andgenerates a detector output signal indicative of the detected phasedifferences. The charge pump receives the detector output signal andgenerates a set of phase error signals (e.g., UP and DOWN currents fedinto the filter). The loop filter filters the phase error signals togenerate a control signal that is then used to adjust the frequency ofthe VCO such that the phases of the two signals provided to the phasedetector are locked. When the phases of the two signals are locked, therespective frequencies of the two signals are exactly the same.

[0006]FIG. 1 is a simplified block diagram of a conventional phaselocked loop 10. An input signal is provided to a phase detector 12 thatalso receives a reference signal from a divider 20. The input signal canbe a clock signal, a data stream, or some other types of signal havingphase and/or frequency information to which the phase locked loop can belocked. The reference signal is typically a clock signal used to triggerthe phase detector 12. Phase detector 12 generates an output signalindicative of the timing differences (i.e., the phase differences)between the input signal and the reference signal. The output signalfrom the phase detector 12 is provided to a charge pump 14 thatgenerates an output signal indicative of the detected phase errorbetween the input and reference signals. In some designs, the chargepump output signal is logic high if the phase of the input signal isearly (or late) relative to that of the reference signal, logic low ifthe phase of the input signal is late (or early) relative to that of thereference signal, and tri-stated for a period of time between clockedges.

[0007] The charge pump output signal is provided to a loop filter 16that filters the signal with a particular transfer characteristic togenerate a control signal. The control signal is then provided to, andused to control the frequency of, a voltage-controlled oscillator (VCO)18. VCO 18 generates an output clock having a frequency can be adjustedby the control signal at the input of VCO. The output clock is providedto divider 20 that divides the frequency of the output clock by a factorof N to generate the reference signal. Divider 20 is optional and notused when the frequency of the output clock is the same as that of theinput signal (i.e., N=1). The control signal adjusts the frequency ofVCO 18 such that the frequencies of the two signals provided to phasedetector 12 are locked when the phase locked loop 10 is locked.

[0008] In typical PLLs, signals are transmitted between components in anon-differential manner. Signals transmitted in this manner, however,are subject to a number of shortcomings. For example, noise from powersupply fluctuations and substrate can relatively easily affect thequality of such signals causing jitters and other problems. Hence, itwould be desirable to implement the PLL in a fully differentialarchitecture that would significantly reduce jitter and improve overallnoise performance.

[0009] Furthermore, modern day devices and applications continuallydemand improved performance criteria including high speed, low powerdissipation, and low cost, from their constituent components. To realizeand meet such performance criteria, it would be desirable to implementthe PLL in low-cost CMOS technology that allows for increased levels ofintegration.

SUMMARY OF THE INVENTION

[0010] The present invention relates specifically to a fullydifferential phase-locked loop. In one embodiment, the phase-locked loopincludes a phase-frequency detector, a Gm cell block, a low pass filterand a voltage controlled oscillator. These various elements of thephase-locked loop are connected to one another in a fully differentialmanner, i.e., each element has an input and/or an output each having atleast a differential signal. In one embodiment, each of these variouselements of the phase-locked loop is implemented using high speedcurrent-controlled complementary metal-oxide-semiconductor (C³MOS)logic.

[0011] Accordingly, in an exemplary embodiment, an improved phase-lockedloop is provided including: a detector configured to receive an inputsignal and a reference signal and to provide a detector output signalindicative of a difference between the input signal and the referencesignal; a signal filter coupled to the detector and configured toreceive the detector output signal and to provide a control signal; anda voltage controller oscillator coupled to the signal filter andconfigured to receive the control signal and to provide an oscillatorsignal which is adjustable based on the control signal, the oscillatorsignal is fed back to the detector as the reference signal; wherein thedetector, the signal filter, and the voltage controller oscillator areconnected to one another in a fully differential manner.

[0012] Optionally, a transconductance (or Gm) cell circuit is disposedbetween the detector and the signal filter and configured to provide acurrent output signal to the signal filter; and a divider circuit isdisposed between the voltage controlled oscillator and the detector andconfigured to provide a divided version of the oscillator signal to thedetector.

[0013] Accordingly, in another exemplary embodiment, a method forimplementing a phase-locked loop having a plurality of componentsincluding a detector, a transconductance (or Gm) cell, a signal filter,a voltage controlled oscillator and a divider circuit is provided,comprising: connecting each of the plurality of components to oneanother in a differential manner; and implementing each of the pluralityof components using C³MOS logic.

[0014] Reference to the remaining portions of the specification,including the drawings and claims, will realize other features andadvantages of the present invention. Further features and advantages ofthe present invention, as well as the structure and operation of variousembodiments of the present invention, are described in detail below withrespect to accompanying drawings, like reference numbers indicateidentical or functionally similar elements.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a simplified schematic block diagram of a conventionalphase locked loop;

[0016]FIG. 2 is a simplified schematic block diagram of a phase lockedloop according to one exemplary embodiment of the present invention;

[0017]FIG. 3 is a simplified schematic block diagram of a differentialphase-frequency detector according to one exemplary embodiment of thepresent invention;

[0018]FIG. 4 is a simplified circuit diagram of a differential Gm cellblock according to one exemplary embodiment of the present invention;and

[0019]FIG. 5 is a simplified schematic block diagram of a differentialvoltage controlled oscillator according to one exemplary embodiment ofthe present invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

[0020] The present invention will now be described. Referring to FIG. 2,there 20 is shown a simplified schematic block diagram of a PLL 100according to one exemplary embodiment of the present invention.According to this exemplary embodiment, PLL 100 is fully differentialand is implemented in standard CMOS processing technology usingcurrent-controlled CMOS (or C³MOS) logic. Using C³MOS logic allows forhigher degree of integration which, in turn, leads to high 25 speedsignal processing and lower cost.

[0021] Various embodiments for circuitry implemented using C³MOS logicare described in detail in commonly-assigned U.S. patent applicationSer. No. 09/484,856, entitled “Current-Controlled CMOS Logic Family,” toA. Hairapetian, filed on Jan. 18, 2000, now U.S. Pat. No. 6,424,194 B1,which is hereby incorporated by reference for all purposes. As describedtherein, the basic building block of the C³MOS logic family uses a pairof conventional MOSFETs that steer current between a pair of loaddevices in response to a difference between a pair of input signals.Thus, unlike conventional CMOS logic, C³MOS logic dissipates staticcurrent and is able to operate at much higher speeds.

[0022] The C³MOS logic family contains all the building blocks of otherlogic families. Examples of such building blocks include inverters,buffers, level shift buffers, N-input NOR and NAND gates, exclusive OR(XOR) gates, flip flops and latches, and the like. More complex logiccircuits such as shift registers, counters, frequency dividers, etc.,can be constructed in C³MOS using the basic logic elements. Based on thedisclosure and teaching provided in U.S. patent application Ser. No.09/484,856, as identified above, it should be apparent to a person ofordinary skill in the art to be able to use C³MOS logic to designcomplex logic circuits.

[0023] As shown in FIG. 2, in an exemplary embodiment, the PLL 100includes a differential input buffer BUFF 102, a differentialphase-frequency detector PFD 104, a Gm cell block 106, a low pass filter108, a voltage controller oscillator VCO 110 and a divider 112. As willbe further described below, these various elements of the PLL 100 areconnected to one another in a fully differential manner. In other words,each of the elements of the PLL 100 has at least a differential inputcomprising two constituent input signals and a differential outputcomprising two constituent output signals. It should be understood thata differential signal inherently includes two constituent signals.

[0024] The PLL 100 receives a differential input signal, including twoinput clock signals REFCKP and REFCKN, at the differential input buffer102. The differential input buffer 102 amplifies and conditions the twoinput clock signals REFCKP and REFCKN while maintaining theirdifferential nature. The differential input buffer 102 is preferablyimplemented in C³MOS logic. By implementing the differential inputbuffer 102 in C³MOS, good common mode rejection and high slew rate earlbe achieved. The use of buffer 102, however, is optional.

[0025] The differential phase-frequency detector 104 then receives thedifferential input signal as well as a differential reference signal,including signals FBCKN and FBCKP, from the differential input buffer102 and the divider 112 respectively. The phase-frequency detector 104detects the difference, if any, in the phase/frequency of thedifferential input clock signal and the differential reference signaland accordingly generates two differential detector output signalscomprising two pairs of output signals in the form of complementary UPor DN signals. It should be noted that each of the complementary UP andDN differential signals is made up of a pair of signals UP/UPB andDN/DNB respectively.

[0026]FIG. 3 shows an exemplary implementation for the differentialphase-frequency detector 104. In this exemplary implementation, thedifferential phase-frequency detector 104 includes a pair of resetableflip-flops RFF 200 and 202, a chain of buffers 206 and an AND logicfunction implemented in the form of an AND gate 204. Preferably, thesevarious circuit elements in the differential phase-frequency detector104 are implemented using C³MOS logic.

[0027] Resetable flip-flops 200 and 202 receive differential signals atREFP/REFN and FBP/FBN inputs from the differential input buffer 102 andthe divider 112, respectively. AND gate 204 then logically combines thefour outputs UP/UPB and DN/DNB from the two resetable flip-flops 200 and202 to generate the reset signal RST which is eventually fed back to thetwo flip-flops 200 and 202. The chain of buffers 206 add apre-determined amount of delay before the reset signal RST is applied tothe flip-flops 200 and 202 to avoid a too narrow reset signal RST.

[0028] Referring back to FIG. 2, the differential detector outputsignals from the phase-frequency detector 104 are then fed to the Gmcell block 106. The Gm cell block 106 operates to convert a voltageinput signal to a current output signal which is indicative of thedetected phase/frequency error, if any, between the two differentialsignals received by the differential phase-frequency detector 104. Apre-filter may be optionally included between the outputs of thephase-frequency detector 104 and the inputs of the Gm cell 106 to adjustsignal levels for C³MOS logic levels, if desired.

[0029]FIG. 4 is an exemplary circuit implementation for a fullydifferential Gm cell block 106. Under this exemplary implementation, theGm cell block 106 includes an amplifier stage 300 made up of a pair ofdifferential inputs that receives signals DN/DNB and UP/UPB from thedifferential phase-frequency detector 104, and current source and loaddevices. More specifically, the amplifier stage 300 is connected to acommon-mode feedback (CMFB) circuit 302. Preferably, the Gm cell block106 is fully differential and is implemented using C³MOS technology.Detailed description of one embodiment of a Gm cell block 106 for use inthe PLL 100 of the present invention is provided in commonly assignedU.S. patent application Ser. No. 09/540,243, entitled “Gm cell basedPhase Locked Loops,” by Gutierrez et al., filed on Mar. 31, 2000, nowU.S. Pat. No. 6,526,113 B1, which is hereby incorporated in itsentirety.

[0030] Referring back to FIG. 2, the Gm cell block 106 combines with thelow pass filter LPF 108 to form an ideal integrator. The low pass filter108 is a differential filter made of, for example, an RC network thatcan be either integrated with the rest of the circuitry or placed offchip. Since the output of the Gm cell block 106 is a differentialcurrent signal, feeding the output of the Gm cell block 106 to the lowpass filter 108 causes voltage potential to develop at signals VCP andVCN which represent a differential voltage signal.

[0031] The differential voltage signal, represented by VCP and VCN, atthe output of the Gm cell block 106 are then applied to the differentialvoltage controlled oscillator 110 to control the frequency of adifferential oscillator output which is comprised of signals CLKP andCLKN. When the PLL 100 is locked, the voltage controlled oscillator 110generates a differential oscillator output having a frequency that islocked to that of the differential input signal, REFCKP and REFCKN.

[0032]FIG. 5 is a simplified schematic block diagram showing anexemplary implementation of the fully differential voltage controlledoscillator 110. As shown in FIG. 5, the voltage controlled oscillator110 is implemented in the form of a differentially tunedvaractor-inductor oscillator. Such an exemplary oscillator is describedin greater detail in commonly assigned U.S. patent application Ser. No.09/792,684, filed on Feb. 24, 2001, entitled “Method and Circuitry forImplementing a Differentially Tuned Varactor-Inductor Oscillator,” toGutierrez, which is hereby incorporated by reference in its entirety.

[0033] The differential oscillator output of the voltage controlledoscillator 110 is then fed to divider 112, if necessary. Since thevoltage controlled oscillator 110 usually operates at a high frequency,e.g., 32 times the input signal frequency, the frequency of thedifferential oscillator output may need to be reduced before it isprovided to the phase-frequency detector 104. The divider 112 is usedfor this frequency-reduction purpose.

[0034] The divider or divide by N (+N) circuit 112 receives thedifferential oscillator output of the voltage controlled oscillator 110.The divider 112 then divides the signal frequency down to the inputfrequency (e.g., +32), generating signals FBCKN and FBCKP, whichrepresent a divided version of the differential oscillator output, whichare fed back to the phase-frequency detector 104. Preferably, thedivider 112 is also implemented using differential C³MOS logic.

[0035] As thus constructed, a fully differential PLL using C³MOS logicexhibits a number of performance advantages over prior art PLLsincluding higher speed, reduced noise and ease of integration.

[0036] It is understood that the examples and embodiments describedherein are for illustrative purposes only and that various modificationsor changes in light thereof will be suggested to persons skilled in theart and are to be included within the spirit and purview of thisapplication and scope of the appended claims. All publications, patents,and patent applications cited herein are hereby incorporated byreference for all purposes in their entirety.

What is claimed is:
 1. A differential phase-locked loop comprising: adifferential detector configured to receive an input signal and areference signal and to provide a detector output signal indicative of adifference between the input signal and the reference signal; adifferential signal filter coupled to the detector and configured toreceive the detector output signal and to provide a control signal; anda differential voltage controlled oscillator coupled to the signalfilter and configured to receive the control signal and to provide anoscillator signal which is adjustable based on the control signal, theoscillator signal is fed back to the detector as the input signal;wherein the differential detector, the differential signal filter, andthe differential voltage controlled oscillator are connected to oneanother in a fully differential manner.
 2. The differential phase-lockedloop of claim 1 wherein the differential detector, the differentialsignal filter, and the differential voltage controller oscillator areeach implemented using C³MOS logic.
 3. The differential phase-lockedloop of claim 2 further comprising: a differential Gm cell circuitdisposed between the differential detector and the differential signalfilter and configured to receive the detector output signal and toprovide a current output signal; wherein the current output signal isfed to the differential signal filter; wherein the differential Gm cellcircuit is coupled to the differential detector and the differentialsignal filter in a fully differential manner; and wherein thedifferential Gm cell circuit is implemented using C³MOS logic.
 4. Thedifferential phase-locked loop of claim 2 further comprising: adifferential divider circuit disposed between the differential voltagecontrolled oscillator and the differential detector; wherein thedifferential divider circuit is coupled to the differential voltagecontrolled oscillator and the differential detector in a fullydifferential manner; and wherein the differential divider circuit isimplemented using C³MOS logic.
 5. The differential phase-locked loop ofclaim 1 wherein the differential detector is a differentialphase-frequency detector.
 6. The differential phase-locked loop of claim1 wherein the differential signal filter is a differential lowpassfilter.
 7. The differential phase-locked loop of claim 1 wherein theinput signal, the reference signal, the detector output signal, thecurrent output signal, the control signal and the oscillator signal areimplemented in a differential manner.
 8. The differential phase-lockedloop of claim 1 wherein the differential detector further includes:first and second resetable flip-flops configured to receive a first anda second differential signal respectively; an AND logic functionconfigured to receive differential outputs from the first and secondresetable flip-flops; and one or more buffers configured to receiveoutput from said AND logic function and to provide a reset signal toreset the first and second resetable flip-flops.
 9. An integratedcircuit comprising the differential phase-locked loop of claim
 1. 10. Acommunication system comprising the differential phase-locked loop ofclaim
 1. 11. A phase-locked loop comprising: a detector configured toreceive a differential input signal and a differential reference signaland to provide a differential detector output signal indicative of adifference between the differential input signal and the differentialreference signal; a Gm cell circuit coupled to the detector andconfigured to receive the differential detector output signal and toprovide a differential current output signal; a signal filter coupled tothe Gm cell circuit and configured to receive the differential currentoutput signal and to provide a differential control signal; and avoltage controlled oscillator coupled to the signal filter andconfigured to receive the differential control signal and to provide adifferential oscillator signal which is adjustable based on thedifferential control signal, the differential oscillator signal is fedback to the detector as the differential input signal; wherein thedetector, the GM cell circuit, the signal filter, and the voltagecontrolled oscillator are each implemented using C³MOS logic.
 12. Thephase-locked loop of claim 11 further comprising: a divider circuitdisposed between the voltage controlled oscillator and the detector;wherein the divider circuit is configured to receive the differentialoscillator signal and to provide a differential divided signal to be fedto the detector as the differential input signal; and wherein thedivider circuit is implemented using C³MOS logic.
 13. The phase-lockedloop of claim 11 wherein the detector is a phase-frequency detector. 14.The phase-locked loop of claim 11 wherein the signal filter is a lowpassfilter.
 15. The phase-locked loop of claim 11 wherein the detectorfurther includes: first and second resetable flip-flops configured toreceive a first and a second differential signal respectively; an ANDlogic function configured to receive differential outputs from the firstand second resetable flip-flops; and one or more buffers configured toreceive output from said AND logic function and to provide a resetsignal to reset the first and second resetable flip-flops.
 16. Anintegrated circuit comprising the phase-locked loop of claim
 11. 17. Acommunication system comprising the phase-locked loop of claim
 11. 18. Aphase-locked loop comprising: a detector configured to receive an inputsignal and a reference signal and to provide a detector output signalindicative of a difference between the input signal and the referencesignal; a Gm cell circuit coupled to the detector and configured toreceive the detector output signal and to provide a current outputsignal; a signal filter coupled to the Gm cell circuit and configured toreceive the current output signal and to provide a control signal; avoltage controlled oscillator coupled to the signal filter andconfigured to receive the control signal and to provide an oscillatorsignal which is adjustable based on the control signal; and a dividercircuit coupled to the voltage controlled oscillator and configured toreceive the oscillator signal and to provide a divided version of theoscillator signal to be fed to the detector as the input signal; whereinthe detector, the Gm cell circuit, the signal filter, the voltagecontrolled oscillator and the divider circuit are connected to oneanother in a fully differential manner; and wherein the detector, the Gmcell circuit, the signal filter, the voltage controlled oscillator andthe divider circuit are implemented using C³MOS logic.
 19. Thephase-locked loop of claim 18 wherein the differential detector furtherincludes: first and second resetable flip-flops configured to receive afirst and a second differential signal respectively; an AND logicfunction configured to receive differential outputs from the first andsecond resetable flip-flops; and at least one buffer configured toreceive differential output from the AND logic function and to provide areset signal to reset the first and second resemble flip-flops.
 20. Amethod for implementing a phase-locked loop having a plurality ofcomponents including a detector, a signal filter, a voltage controlledoscillator and a divider circuit, comprising: connecting each of saidplurality of components to one another in a differential manner; andimplementing each of said plurality of components using C³MOS logic. 21.A method for implementing a phase-locked loop, comprising: providing adifferential input signal and a differential reference signal to adetector; providing a differential detector output signal from thedetector as input to a signal filter; providing a differential controlsignal from the signal filter as input to a voltage controlledoscillator; and providing a differential oscillator signal from thevoltage controlled oscillator as the input signal to the detector. 22.The method of claim 21 further comprising: implementing the detector,the signal filter and the voltage controlled oscillator using C³MOSlogic.
 23. The method of claim 21 further comprising: disposing a Gmcell circuit between the detector and the signal filter; providing thedifferential detector output signal from the detector as input to the Gmcell circuit; and providing a differential current output signal fromthe Gm cell circuit as input to the signal filter.
 24. The method ofclaim 23 further comprising: implementing the Gm cell circuit usingC³MOS logic.
 25. The method of claim 21 further comprising: disposing adivider circuit between the voltage controlled oscillator and thedetector; providing the differential oscillator signal from the voltagecontrolled oscillator as input to the divider circuit; and providing adivided version of the differential oscillator signal from the dividercircuit as the differential input signal to the detector.
 26. The methodof claim 25 further comprising: implementing the divider circuit usingC³MOS logic.
 27. A method for implementing a phase-locked loop,comprising: providing a differential input signal and a differentialreference signal to a detector; providing a differential detector outputsignal from the detector as input to a Gm cell circuit; providing adifferential current output signal from the Gm cell circuit as input toa signal filter; providing a differential control signal from the signalfilter as input to a voltage controlled oscillator; providing adifferential oscillator signal from the voltage controlled oscillator asinput to a divider circuit; providing a divided version of thedifferential oscillator signal from the divider circuit as thedifferential input signal to the detector; and implementing thedetector, the Gm cell circuit, the signal filter, the voltage controlledoscillator and the divider circuit using C³MOS logic.